 |
TTTC's Electronic Broadcasting Service |
|
IEEE International Symposium on Defect and Fault Tolerance in VLSI and Nanotechnology Systems
|
SUBMISSION DEADLINE EXTENDED TO MAY 7, 2016
|
|
|
CALL FOR PAPERS
|
|
|
DFT is an annual Symposium providing an open forum for presentations in the field of defect and fault tolerance in digital systems inclusive of emerging technologies. One of the unique features of this symposium is to combine new academic research with state-of-the-art industrial data, necessary ingredients for significant advances in this field. All aspects of design, manufacturing, test, reliability, and availability that are affected by defects during manufacturing and by faults during system operation are of interest. The topics include (but are not limited to) the following ones: 1. Yield Analysis and Modeling: Defect/fault analysis and models; statistical yield modeling; critical area and other metrics. 2. Testing Techniques: Built-in self-test; delay fault modeling and diagnosis; testing for analog and mixed circuits; signal and clock integrity. 3. Design For Testability in IC Design: FPGA, SoC, NoC, ASIC, microprocessors. 4. Error Detection, Correction, and Recovery: Self-testing and self-checking design; error-control coding; fault masking and avoidance; recovery schemes, space/time redundancy; hw/sw techniques, architectural-specific techniques, system-level strategies. 5. Dependability Analysis and Validation: Fault injection techniques and environments; dependability characterization; aging modeling and analysis. 6. Repair, Restructuring and Reconfiguration: Repairable logic; reconfigurable circuit design; DFT for on-line operation; self-healing; reliable FPGA-based systems. 7. Defect and Fault Tolerance: Reliable circuit/system synthesis; radiation hardened/tolerant processes and design; design space exploration for dependable systems, transient/soft faults and errors; aging management and recovery strategies. 8. Fail-Safe Design for Critical Applications: Methodologies and case study applications to automotive, railway, avionics, industrial control, biomedicine, space and smart power networks. 9. Emerging Technologies: Techniques for CNTs, QCA, DNA, RTDs, SETs, molecular devices and self-assembly. 10. Design for Security: Fault attacks, fault tolerance-based countermeasures, Scan-based attacks and countermeasures, side-channel attack and countermeasures, hardware Trojans, security vs. reliability trade-offs, interaction between VLSI test, trust, and reliability. |
|
|
Prospective authors are invited to submit original and unpublished contributions. Two types of submissions are possible: (i) regular papers (6 pages), and (ii) short papers (4 pages). Both types will be included in the symposium proceedings and should adhere to the IEEE conference template, 2-columns style (available on conference web site), and submitted as PDF file, electronically. Detailed information about the submission process are available on the conference website. Proposals for special sessions are also invited this year. For more information, visit symposium website. |
|
|
Paper registration deadline: April 29, 2016 Paper submission deadline: May 7, 2016 April 29, 2016 Acceptance notification: July 1, 2016 Camera ready deadline: July 22, 2016 |
|
| Additional Information | |
|
General co-chairs:
Program co-chairs:
Industrial liaison chair:
Publicity chair:
Publication co-chairs:
|
|
| Committee | |
|
Program Committee
|
|
| For more information, visit us on the web at: http://www.dfts.org/ |
|
|
The CONFERENCE is sponsored by the Institute of Electrical and Electronics Engineers (IEEE) Computer Society's Test Technology Technical Council (TTTC). |
|
IEEE
Computer Society- Test Technology Technical Council |
||
|
TTTC CHAIR
PAST CHAIR
TTTC 1ST VICE CHAIR
SECRETARY
ITC GENERAL CHAIR TEST WEEK COORDINATOR TUTORIALS AND EDUCATION STANDARDS EUROPE MIDDLE EAST & AFRICA STANDING COMMITTEES ELECTRONIC MEDIA |
PRESIDENT OF BOARD SENIOR PAST CHAIR TTTC 2ND VICE CHAIR FINANCE IEEE DESIGN & TEST EIC TECHNICAL MEETINGS TECHNICAL ACTIVITIES ASIA & PACIFIC LATIN AMERICA NORTH AMERICA COMMUNICATIONS INDUSTRY ADVISORY BOARD |
|
This message contains public information only. You are invited to copy and distribute it further. For more information contact the TTTC office or visit http://tab.computer.org/tttc/ To remove or modify your contact information, or to register new users, please click here and follow the on-line instructions. |